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7-173 features ? single 2.7-3.6 volt supply ? programmable m- law/a-law codec and ?lters ? fully differential to output driver ? ssi digital interface ? individual transmit and receive mute controls ? 0db gain in receive path ? 6db gain in transmit path ? low power operation ? itu-t g.714 compliant applications ? cellular radio sets ? local area communications stations ? line cards ? battery operated equipment description the mt91l62 3v single rail codec incorporates a built-in filter/codec, transmit anti-alias ?lter, a reference voltage and bias source. the device supports both a-law and m -law requirements. the mt91l62 is a true 3v device employing a fully differential architecture to ensure wide dynamic range. an analog output driver is provided, capable of driving a 20k ohm load. the mt91l62 is fabricated in mitel's iso 2 -cmos technology ensuring low power consumption and high reliability. ordering information mt91l62ae 20 pin plastic dip (300 mil) mt91l62as 20 pin soic mt91l62an 20 pin ssop -40 c to +85 c figure 1 - functional block diagram ain+ ain- aout + aout - filter/codec gain encoder decoder 6db 0 db analog interface pcm serial interface timing control vdd vssa vbias vref din dout stb clockin pwrst ic a / m csl0 csl1 csl2 rxmute txmute ds5179 issue 4 august 1999 mt91l62 3 volt single rail codec iso 2 -cmos advance information
mt91l62 advance information 7-174 figure 2 - pin connections pin description pin # name description 13 v bias bias voltage (output). (v dd /2) volts is available at this pin for biasing external ampli?ers. connect 0.1 m f capacitor to v ss . 14 v ref reference voltage for codec (output). nominally [(v dd /2)-1.1] volts. used internally. connect 0.1 m f capacitor to v ss . 15 pwrst power-up reset. resets internal state of device via schmitt trigger input (active low). 16 ic internal connection. tie externally to v ss for normal operation. 17 a/ m a/ m law selection . cmos level compatable input pin governs the companding law used by the device. a-law selected when pin tied to v dd or m -law selected when pin tied to v ss . 18 rxmute receive mute. when 1, the transmit pcm is forced to negative zero code. when 0, normal operation. cmos level compatable input. 19 txmute transmit mute. when 1, the transmit pcm is forced to negative zero code. when 0, normal operation. cmos level compatable input. 20 21 22 csl0 csl1 csl2 clock speed select. these pins are used to program the speed of the ssi mode as well as the conversion rate between the externally supplied mcl clock and the 512 khz clock required by a ?lter/codec. refer to table 2 for details. cmos level compatable input. 23 d out data output. a tri-state digital output for 8-bit wide channel data being sent to the layer 1 device. data is shifted out via the pin concurrent with the rising edge of bcl during the timeslot de?ned by stb. 24 d in data input. a digital input for 8-bit wide data from the layer 1 device. data is sampled on the falling edge of bcl during the timeslot de?ned by stb. cmos level compatable input. 13 stb data strobe. this input determines the 8-bit timeslot used by the device for both transmit and receive data. this active high signal has a repetition rate of 8 khz. cmos level compatable input. 14 clockin clock (input). the clock provided to this input pin is used by the internal device functions. connect bit clock to this pin when it is 512 khz or greater. connect a 4096 khz clock to this pin when the bit clock is 128 khz or 256 khz. cmos level compatable input. 15 v dd positive power supply. nominally 3 volts. 16 aout- inverting analog output. (balanced). 17 aout+ non-inverting analog output. (balanced). 18 v ss ground. nominally 0 volts. 19 ain- inverting analog input. no external anti-aliasing is required. 20 ain+ non-inverting analog input. non-inverting input. no external anti-aliasing is required. ain- ain+ vbias vref ic rxmute csl0 csl1 csl2 din dout vss aout + aout - vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 pwrst txmute stb clockin a/ m 20 pin pdip/soic/ssop
advance information mt91l62 7-175 overview the 3v single-rail codec features complete analog/ digital and digital/analog conversion of audio signals (filter/codec) and an analog interface to a standard analog transmitter and receiver (analog interface). the receiver ampli?er is capable of driving a 20k ohm load. functional description filter/codec the filter/codec block implements conversion of the analog 0-3.3 khz speech signals to/from the digital domain compatible with 64 kb/s pcm b-channels. selection of companding curves and digital code assignment are programmable. these are itu-t g.711 a-law or m -law, with true-sign/alternate digit inversion. the filter/codec block also implements a transmit audio path gain in the analog domain. figure 3 depicts the nominal half-channel for the mt91l62. the internal architecture is fully differential to provide the best possible noise rejection as well as to allow a wide dynamic range from a single 3 volt supply design. this fully differential architecture is continued into the analog interface section to provide full chip realization of these capabilities for the external functions. a reference voltage (v ref ), for the conversion requirements of the codec section, and a bias voltage (v bias ), for biasing the internal analog sections, are both generated on-chip. v bias is also brought to an external pin so that it may be used for biasing external gain setting ampli?ers. a 0.1 m f capacitor must be connected from v bias to analog ground at all times. likewise, although v ref may only be used internally, a 0.1 m f capacitor from the v ref pin to ground is required at all times. the analog ground reference point for these two capacitors must be physically the same point. to facilitate this the v ref and v bias pins are situated on adjacent pins. the transmit ?lter is designed to meet itu-t g.714 speci?cations. an anti-aliasing ?lter is included. this is a second order lowpass implementation with a corner frequency at 25 khz. the receive ?lter is designed to meet itu-t g.714 speci?cations. filter response is peaked to compensate for the sinx/x attenuation caused by the 8 khz sampling rate. companding law selection for the filter/codec is provided by the a/ m companding control pin. table 1 illustrates these choices. table 1: law selection analog interfaces standard interfaces are provided by the mt91l62. these are: ? the analog inputs (transmitter), pins ain+/ain-. the maximum peak to peak input is 2.123vpp m- law across ain+/ain- and 2.2vpp a-law across these pins. ? the analog outputs (receiver), pins aout+/ aout-. this internally compensated fully differential output driver is capable of driving a load of 20k ohms. pcm serial interface a serial link is required to transport data between the mt91l62 and an external digital transmission device. the mt91l62 utilizes the strobed data interface found on many standard codec devices. this interface is commonly referred to as simple serial interface (ssi). the bit clock rate is selected by setting the csl2-0 control pins as shown in figure 2. quiet code the pcm serial port can be made to send quiet code to the decoder and receive ?lter path by setting the rxmute pin high. likewise, the pcm serial port will send quiet code in the transmit path when the code itu-t (g.711) m -law a-law + full scale 1000 0000 1010 1010 + zero 1111 1111 1101 0101 -zero (quiet code) 0111 1111 0101 0101 - full scale 0000 0000 0010 1010
mt91l62 advance information 7-176 table 2: bit clock rate selection txmute pin is high. when either of these pins are low their respective paths function normally. the -zero entry of table 1 is used for the quiet code de?nition. ssi mode the ssi bus consists of input and output serial data streams named din and dout respectively, a clock input signal (clockin), and a framing strobe input (stb). a 4.096 mhz master clock is also required for ssi operation if the bit clock is less than 512 khz. the timing requirements for ssi are shown in figures 5 & 6. in ssi mode the mt91l62 supports only b-channel operation. hence, in ssi mode transmit and receive b-channel data are always in the channel de?ned by the stb input. the data strobe input stb determines the 8-bit timeslot used by the device for both transmit and receive data. this is an active high signal with an 8 khz repetition rate. ssi operation is separated into two categories based upon the data rate of the available bit clock. if the bit clock is 512 khz or greater then it is used directly by the internal mt91l62 functions allowing synchronous operation. if the available bit clock is 128 khz or 256 khz, then a 4096 khz master clock is required to derive clocks for the internal mt91l62 functions. applications where bit clock (bcl) is below 512 khz are designated as asynchronous. the mt91l62 will re-align its internal clocks to allow operation when the external master and bit clocks are asynchronous. control pins csl2, csl1 and csl0 are used to program the bit rates. for synchronous operation, data is sampled from din, on the falling edge of bcl during the time slot de?ned by the stb input. data is made available, on csl 2 csl 1 csl 0 external clock bit rate (khz) clockin (khz) 1 0 0 128 4096 1 0 1 256 4096 0 0 0 512 512 0 0 1 1536 1536 0 1 0 2048 2048 0 1 1 4096 4096 figure 3 - audio gain partitioning serial port filter/codec and analog interface pcm receive filter gain 0 db receiver driver 0 db aout + aout- 20k w internal to device external to device default bypass ain+ ain- transmit gain 6 db pcm analog input d in d out decoder encoder
advance information mt91l62 7-177 dout, on the rising edge of bcl during the time slot de?ned by the stb input. dout is tri-stated at all times when stb is not true. if stb is valid, then quiet code will be transmitted on dout during the valid strobe period. there is no frame delay through the pcm serial circuit for synchronous operation. for asynchronous operation dout and din are as de?ned for synchronous operation except that the allowed output jitter on dout is larger. this is due to the resynchronization circuitry activity and will not affect operation since the bit cell period at 128 kb/s and 256 kb/s is relatively large. there is a one frame delay through the pcm serial circuit for asynchronous operation. refer to the speci?cations of figures 5 & 6 for both synchronous and asynchronous ssi timing. pwrst while the mt91l62 is held in pwrst no de vice control or functionality is possible. applications figure 4 shows an application of the mt91l62 in a line card. figure 4 - line card application 0.1 m f 0.1 m f vbias +3v +3v dout din 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 frame pulse clock a/ m mt91l62 100k 100k 100k 100k 100k 100k 100k 1k 1k 1k 1k 1k 1k cs2 cs1 cs0 txmute rxmute timing block output to subscriber line interface input from subscriber line interface 0.1 m f
mt91l62 advance information 7-178 ? exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note 1: power delivered to the load is in addition to the bias current requirements. absolute maximum ratings ? parameter symbol min max units 1 supply voltage v dd - v ss - 0.3 5 v 2 voltage on any i/o pin v i /v o v ss - 0.3 v dd + 0.3 v 3 current on any i/o pin (transducers excluded) i i /i o 20 ma 4 storage temperature t s - 65 + 150 c 5 power dissipation (package) p d 750 mw recommended operating conditions - voltages are with respect to v ss unless otherwise stated characteristics sym min typ max units test conditions 1 supply voltage v dd 2.7 3 3.6 v 2 cmos input voltage (high) v ihc 0.9*v dd v dd v 3 cmos input voltage (low) v ilc v ss 0.1*v dd v 4 operating temperature t a - 40 + 85 c power characteristics characteristics sym min typ max units test conditions 1 static supply current (clock disabled) i ddc1 220 m a outputs unloaded, input signals static, not loaded 2 dynamic supply current: total all functions enabled i ddft 6 10 ma see note 1.
advance information mt91l62 7-179 ? dc electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * note 1 - magnitude measurement, ignore signs. ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 input high voltage cmos inputs v ihc 0.7*vdd v 2 input low voltage cmos inputs v ilc 0.3*vdd v 3 vbias voltage output v bias v dd /2 v max. load = 10k w 4v ref output voltage v ref v dd /2-1.1 v no load 5 input leakage current i iz 0.1 10 m av in =v dd to v ss 6 positive going threshold voltage ( pwrst only) negative going threshold voltage ( pwrst only) hysteresis v t+ v t- 2.2 0.65 0.7 v v v vdd=3v 7 output high current i oh 1.0 ma v oh = 0.9*v dd see note 1 8 output low current i ol 2.5 ma v ol = 0.1*v dd see note 1 9 output leakage current i oz 0.01 10 m av out = v dd and v ss 10 output capacitance c o 15 pf 11 input capacitance c i 10 pf clockin tolerance characteristics ? characteristics min typ ? max units test conditions 1 clockin f requency (asynchronous mode) 4095.6 4096 4096.4 khz (i.e. 100 ppm)
mt91l62 advance information 7-180 ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac characteristics ? for a/d (transmit) path - 0dbm0 = a lo3.17 - 3.17db = 1.027v rms for m -law and 0dbm0 = a lo3.14 - 3.14db =1.067v rms for a-law, at the codec. (v ref =0.4 volts and v bias =1.5 volts.) characteristics sym min typ ? max units test conditions 1 analog input equivalent to overload decision a li3.17 a li3.14 4.246 4.4 vp-p vp-p m -law a-law both at codec 2 absolute half-channel gain m to dout g ax1 5.4 6.0 6.6 db transmit ?lter gain=0db setting. @1020hz 3 gain tracking vs. input level itu-t g.714 method 2 g tx -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db 3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 4 signal to total distortion vs. input level. itu-t g.714 method 2 d qx 35 29 24 db db db 0 to -30 dbm0 -40 dbm0 -45 dbm0 5 transmit idle channel noise n cx n px 13 -70.5 16 -69 dbrnc0 dbm0p m -law a-law 6 gain relative to gain at 1020hz <50hz 60hz 200hz 300 - 3000 hz 3000-3300 hz 3300 hz 3400 hz 4000 hz 4600 hz >4600 hz g rx -0.25 -0.9 -0.9 -1.2 -45 -0.2 -0.6 -23 -41 -25 -30 0.0 0.25 0.25 0.25 0.25 -12.5 -25 -25 db db db db db db db db db db 7 absolute delay d ax 360 m s at frequency of minimum delay 8 group delay relative to d ax d dx 750 380 130 750 m s m s m s m s 500-600 hz 600 - 1000 hz 1000 - 2600 hz 2600 - 2800 hz 9 power supply rejection f=1020 hz pssr 30 50 db 100mv peak signal on v dd m -law
advance information mt91l62 7-181 ? ac electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ac characteristics ? for d/a (receive) path - 0dbm0 = a lo3.17 - 3.17db = 1.027v rms for m -law and 0dbm0 = a lo3.14 - 3.14db =1.067v rms for a-law, at the codec. (v ref =0.4 volts and v bias =1.5 volts.) characteristics sym min typ ? max units test conditions 1 analog output at the codec full scale a lo3.17 a lo3.14 4.183 4.331 vp-p vp-p m -law a-law 1 analog output at the codec full scale. a lo3.17 a lo3.14 4.183 4.331 v p-p v p-p m -law a-law 2 absolute half-channel gain. din to hspkr g ar1 -0.6 0 0.6 db @1020hz 3 gain tracking vs. input level itu-t g.714 method 2 g tr -0.3 -0.6 -1.6 0.3 0.6 1.6 db db db 3 to -40 dbm0 -40 to -50 dbm0 -50 to -55 dbm0 4 signal to total distortion vs. input level. itu-t g.714 method 2 g qr 35 29 24 db db db 0 to -30 dbm0 -40 dbm0 -45 dbm0 5 receive idle channel noise n cr n pr 11.5 -80 14 -77 dbrnc0 dbm0p m -law a-law 6 gain relative to gain at 1020hz 200 hz 300 - 3000 hz 3000 - 3300 hz 3300 hz 3400 hz 4000 hz 4600 hz >4600 hz g rr -0.25 -0.90 -0.9 -0.9 -0.1 -0.5 -23 -41 0.25 0.25 0.25 0.25 0.25 -12.5 -25 -25 db db db db db db db db 7 absolute delay d ar 240 m s at frequency of min. delay 8 group delay relative to d ar d dr 750 380 130 750 m s m s m s m s 500-600 hz 600 - 1000 hz 1000 - 2600 hz 2600 - 2800 hz 9 crosstalk d/a to a/d a/d to d/a ct rt ct tr -90 -90 -74 -80 db db g.714.16 itu-t electrical characteristics ? for analog outputs characteristics sym min typ ? max units test conditions 1 output load impedance e zl 20k ohms across aout 2 allowable output capacitive load e cl 20 pf each pin: aout+, aout-
mt91l62 advance information 7-182 ? electrical characteristics are over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? timing is over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1: not production tested, guaranteed by design. electrical characteristics ? for analog inputs characteristics sym min typ ? max units test conditions 1 maximum input voltage without overloading codec across aout+/aout- v iolh 2.128 2.20 vp-p vp-p a/ m = 0 a/ m = 1 2 input impedance z i 50 k w ain+/ain- to v ss ac electrical characteristics ? - ssi bus synchronous timing (see figure 5) characteristics sym min typ ? max units test conditions 1 bcl clock period t bcl 244 1953 ns bcl=4096 khz to 512 khz 2 bcl pulse width high t bclh 115 122 ns bcl=4096 khz 3 bcl pulse width low t bcll 122 ns bcl=4096 khz 4 bcl rise/fall time t r /t f 20 ns note 1 5 strobe pulse width t enw 8 x t bcl ns note 1 6 strobe setup time before bcl falling t sss 70 t bcl -80 ns 7 strobe hold time after bcl falling t ssh 80 t bcl -80 ns 8 dout high impedance to active low from strobe rising t dozl 55 ns c l =50 pf, r l =1k 9 dout high impedance to active high from strobe rising t dozh 55 ns c l =50 pf, r l =1k 10 dout active low to high impedance from strobe falling t dolz 90 ns c l =50 pf, r l =1k 11 dout active high to high impedance from strobe falling t dohz 90 ns c l =50 pf, r l =1k 12 dout delay (high and low) from bcl rising t dd 80 ns c l =50 pf, r l =1k 13 din setup time before bcl falling t dis 10 ns 14 din hold time from bcl falling t dih 50 ns
advance information mt91l62 7-183 figure 5 - ssi synchronous timing diagram ? timing is over recommended temperature range & recommended power supply voltages. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. note 1:not production tested, guaranteed by design. ac electrical characteristics ? - ssi bus asynchronous timing (note 1) (see figure 6) characteristics sym min typ ? max units test conditions 1 bit cell period t data 7812 3906 ns ns bcl=128 khz bcl=256 khz 2 frame jitter t j 600 ns 3 bit 1 dout delay from stb going high t dda1 t j +600 ns c l =50 pf, r l =1k 4 bit 2 dout delay from stb going high t dda2 600+ t data -t j 600+ t data 600 + t data +t j ns c l =50 pf, r l =1k 5 bit n dout delay from stb going high t ddan 600 + (n-1) x t data -t j 600 + (n-1) x t data 600 + (n-1) x t data +t j ns c l =50 pf, r l =1k n=3 to 8 6 bit 1 data boundary t data1 t data -t j t data +t j ns 7 din bit n data setup time from stb rising t su t data \2 +500ns-t j +(n-1) x t data ns n=1-8 8 din data hold time from stb rising t ho t data \2 +500ns+t j +(n-1) x t data ns (bcl) din dout stb 70% 30% 70% 30% 70% 30% 70% 30% t bclh t r t f t bcll t dis t dih t dozl t dd t bcl t dozh t sss t enw t ssh t dolz t dohz note: levels refer to % v dd (cmos i/o) clockin
mt91l62 advance information 7-184 figure 6 - ssi asynchronous timing diagram din dout stb 70% 30% 70% 30% 70% 30% t j t dda1 note: levels refer to % v dd (cmos i/o) t dha1 t data1 t dda2 t data bit 1 bit 2 bit 3 d1 d2 d3 t ho t su t data /2 t data t data
package outlines small shrink outline package (ssop) - n suf?x pin 1 a 1 b e d e a l h c a 2 dim 20-pin 24-pin 28-pin 48-pin min max min max min max min max a 0.079 (2) - 0.079 (2) 0.079 (2) 0.095 (2.41) 0.110 (2.79) a 1 0.002 (0.05) 0.002 (0.05) 0.002 (0.05) 0.008 (0.2) 0.016 (0.406) b 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.0087 (0.22) 0.013 (0.33) 0.008 (0.2) 0.0135 (0.342) c 0.008 (0.21) 0.008 (0.21) 0.008 (0.21) 0.010 (0.25) d 0.27 (6.9) 0.295 (7.5) 0.31 (7.9) 0.33 (8.5) 0.39 (9.9) 0.42 (10.5) 0.62 (15.75) 0.63 (16.00) e 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.2 (5.0) 0.22 (5.6) 0.291 (7.39) 0.299 (7.59) e 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) 0.025 bsc (0.635 bsc) a 2 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.065 (1.65) 0.073 (1.85) 0.089 (2.26) 0.099 (2.52) h 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.29 (7.4) 0.32 (8.2) 0.395 (10.03) 0.42 (10.67) l 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.022 (0.55) 0.037 (0.95) 0.02 (0.51) 0.04 (1.02) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) ref. jedec standard m0-150/m0118 for 48 pin 5) a & b maximum dimensions include allowable mold flash general-11
package outlines lead soic package - s suf?x notes: 1. controlling dimensions in parenthesis ( ) are in millimeters. 2. converted inch dimensions are not necessarily exact. dim 16-pin 18-pin 20-pin 24-pin 28-pin min max min max min max min max min max a 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) 0.093 (2.35) 0.104 (2.65) a 1 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) 0.004 (0.10) 0.012 (0.30) b 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.030 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) 0.013 (0.33) 0.020 (0.51) c 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) 0.009 (0.231) 0.013 (0.318) d 0.398 (10.1) 0.413 (10.5) 0.447 (11.35) 0.4625 (11.75) 0.496 (12.60) 0.512 (13.00) 0.5985 (15.2) 0.614 (15.6) 0.697 (17.7) 0.7125 (18.1) e 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) 0.291 (7.40) 0.299 (7.40) e 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) h 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) 0.394 (10.00) 0.419 (10.65) l 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) 0.016 (0.40) 0.050 (1.27) pin 1 a 1 b e e a l h c notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) a & b maximum dimensions include allowable mold flash d l 4 mils (lead coplanarity) general-7
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.

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